A memory cell array of a semiconductor memory device generally has a structure in which a plurality of memory cells are formed in a two-dimensional plane on a silicon substrate. In order to increase memory capacity, each memory cell must be manufactured to include increasingly smaller, and more closely packed together, features. However, making the memory cell features smaller becomes a challenge in terms of cost and technique.
To solve the above-mentioned challenge, a technique of manufacturing a three-dimensional stacked memory device by three-dimensionally stacking a plurality of memory layers and processing these memory layers collectively is proposed.
As one type of this collectively-processed three-dimensional stacked memory, a pipe-shaped NAND flash memory in which a plurality of NAND strings are formed in a U-shape in the direction in which the layers are stacked is proposed. In the U-shaped NAND flash memory, one NAND string is formed as a pair of silicon pillars (a pair of columnar portions) and a pipe (a joining portion) joins and electrically connects the pair of silicon pillars at a lower end thereof. The pipe portion of the NAND string is coupled to a back-gate layer.
The process of forming the collectively-processed three-dimensional stacked memory includes, for example, forming a stacked body formed of a plurality of electrode layers functioning as control gate electrodes, and a plurality of insulating layers alternately stacked with the electrode layers. The process also includes, for example, forming a memory hole in the stacked body, forming a charge storage film on the side wall of the memory hole, and then forming a silicon pillar inside the memory hole.
However, when the number of electrode layers and insulating layers (the number of stacked electrode layers and insulating layers) forming the stacked body is increased, the processing of the stacked body to form a hole therein becomes a challenge. As a result, process variation and device characteristic variations tend to arise.